CDAC Recruitment 2025 for 280 Posts

Center for Development of Advanced Computing (CDAC) has published recruitment notification for 280 posts, eligible candidate can apply online on or before 31st July 2025, details regarding post, educational qualification and how to apply is as mentioned below.

CDAC Recruitment 2025 for 280 Posts

Advertisement No.: CORP/ACR/02/2025

Last Date to Apply: 31st July 2025

Total No. Of Post: 361 Posts

Name of the Post & Details:

Post No.	Name of the Post	No. of Vacancy
1	Design Engineer-E1	203
2	Senior Design Engineer-E2	67
3	Principal Design Engineer-E3	05
4	Technical Manager-E4	03
5	Senior Technical Manager-E5	01
6	Chief Technical Manager-E6	01
Total No. Of Post		280

Educational Qualification:

• Design Engineer-E1: (i) BE/B.Tech (Electronics, Computer Science, Information Technology, Information Science) with 60% marks or PG Diploma (VLSI, HPC, Embedded Systems, Artificial Intelligence-AI /Machine Learning-ML) or B.Sc with MCA / BCA or M.Sc (Computer Science, Electronics, Mathematics) or ME/M.Tech (Microelectronics/ VLSI, Electronic System Design, Computer Science, Artificial Intelligence / Machine learning, Applied Mathematics, Photonics) or Ph. D (Microelectronics / VLSI, Computer Science , Artificial Intelligence-AI /Machine Learning-ML, Photonics (ii) Up to 03 years of experience
• Senior Design Engineer-E2: (i) BE/B.Tech ( Electronics, Computer Science, Information Technology, Information Science) with 60% marks or PG Diploma ( VLSI, HPC, Embedded Systems, Artificial Intelligence-AI /Machine Learning-ML) or B.Sc with MCA / BCA or M.Sc (Computer Science, Electronics, Mathematics) or ME/M.Tech (Microelectronics/ VLSI, Electronic System Design, Computer Science, Artificial Intelligence / Machine learning, Applied Mathematics, Photonics) or Ph. D (Microelectronics / VLSI, Computer Science , Artificial Intelligence-AI /Machine Learning-ML, Photonics (ii) 03 to 06 years of experience
• Principal Design Engineer-E3: (i) B.E./B.Tech (Electronics) or PG Diploma (VLSI) with 60% marks or M.Sc (Electronics, Mathematics) or M.E / M Tech (Microelectronics/VLSI, Electronic System Design, Applied Mathematics) or Ph.D (Microelectronics / VLSI) (ii) 06 to 09 years of experience
• Technical Manager-E4: (i) B.E./B.Tech (Electronics) or PG Diploma (VLSI) with 60% marks or M.Sc (Electronics, Mathematics) or M.E / M Tech (Microelectronics/VLSI, Electronic System Design, Applied Mathematics) or Ph.D (Microelectronics / VLSI) (ii) 09 to 13 years of experience
• Senior Technical Manager-E5: (i) B.E./B.Tech (Electronics) or PG Diploma (VLSI) with 60% marks or M.Sc (Electronics, Mathematics) or M.E / M Tech (Microelectronics/VLSI, Electronic System Design, Applied Mathematics) or Ph.D (Microelectronics / VLSI) Mathematics) or Ph.D (Microelectronics / VLSI) (ii) 13 to 18 years of experience
• Chief Technical Manager-E6: (i) B.E./B.Tech (Electronics) or PG Diploma (VLSI) with 60% marks or M.Sc (Electronics, Mathematics) or M.E / M Tech (Microelectronics/VLSI, Electronic System Design, Applied Mathematics) or Ph.D (Microelectronics / VLSI) (ii) 18 years of experience

Age Limit: [SC/ST: 05 Years Relaxation, OBC: 03 Years Relaxation]

• Design Engineer-E1: 30 years
• Senior Design Engineer-E2: 33 years
• Principal Design Engineer-E3: 37 years
• Technical Manager-E4: 41 years
• Senior Technical Manager-E5: 46 years
• Chief Technical Manager-E6: 50-65 years

Job Location: All India

Fee: No fee

Official Website: www.cdac.in

Official Notification: Click here

How to Apply: Click here

Important Dates:

• Starting Date to Apply: 5 July 2025
• Last Date of Online Application: 31st July 2025